In Proceedings of International Intersociety Electronic and Photonic Packaging Conference (INTERpack '97), 113–7. ... “Sensitivity Analysis of Multiconductor Transmission Lines and Optimization for High-Speed Interconnect Circuit Design ...
S. Yamamichi , Y. Muramatsu , P.Y. Lesaicherre , and H. Ono , Jpn . J. Appl . Phys . 34 , 5188 ( 1995 ) 12.9 . H.J. Osten , J.P. Liu , H.J. Mussig , and P. Zaumseil , Microelectr . Reliab . 41 , 991 ( 2001 ) 12.10 .
... Technical Digest , 934 ( 1999 ) . 13. T. Mizuno , et al , IEEE Electron Device Letters , 21 , 230 ( 2000 ) . 14. N ... Technical Digest , 737 ( 2001 ) . 41. K. Rim , et al , IEEE VLSI Symp . , Digest of Tech . Papers , 210 ( 2001 ) . 42 ...
Ferry DK and Goodnick SM (1997) Transport in Nanostructures. Cambridge: Cambridge University Press. Heinzel T (2003) Mesoscopic Electronics in solid state nanostructures. Weinheim: Wiley-VCH. Ihn T (2004) Electronic Quantum Transport in ...
... Technical Digest, Washington DC, 2005, pp. 873–876. 49. R. Ohba, Y. Mitani, N. Sugiyama et al., 25nm planar bulk SONOS-type memory with double tunnel junction, Electron Devices Meeting, IEEE IEDM Technical Digest, San Francisco CA, 2006 ...